hwtBuildsystem.vivado package

Subpackages

• hwtBuildsystem.vivado.api package
  • ConfigErr
  • FILE_TYPE
    • FILE_TYPE.EDIF
    • FILE_TYPE.NGC
    • FILE_TYPE.SYSTEMVERILOG
    • FILE_TYPE.TCL
    • FILE_TYPE.VERILOG
    • FILE_TYPE.VERILOG_HEADER
    • FILE_TYPE.VHDL
    • FILE_TYPE.VHDL_2008
  • Language
    • Language.verilog
    • Language.vhdl
  • Submodules
  • hwtBuildsystem.vivado.api.boardDesign module
    • VivadoBoardDesign
      • VivadoBoardDesign.create()
      • VivadoBoardDesign.delete()
      • VivadoBoardDesign.exist()
      • VivadoBoardDesign.exportToTCL()
      • VivadoBoardDesign.importFromTcl()
      • VivadoBoardDesign.insertPort()
      • VivadoBoardDesign.mkWrapper()
      • VivadoBoardDesign.open()
      • VivadoBoardDesign.regenerateLayout()
      • VivadoBoardDesign.setAsTop()
      • VivadoBoardDesign.unit()
  • hwtBuildsystem.vivado.api.net module
    • VivadoBoardDesignNet
      • VivadoBoardDesignNet.create()
      • VivadoBoardDesignNet.createMultipleFromDict()
  • hwtBuildsystem.vivado.api.pin module
    • VivadoBoardDesignPin
      • VivadoBoardDesignPin.get()
  • hwtBuildsystem.vivado.api.port module
    • VivadoBoardDesignPort
      • VivadoBoardDesignPort.create()
      • VivadoBoardDesignPort.forEachBit()
      • VivadoBoardDesignPort.fromInterface()
      • VivadoBoardDesignPort.get()
  • hwtBuildsystem.vivado.api.project module
    • VivadoProject
      • VivadoProject.SUFFIX_TO_FILE_TYPE
      • VivadoProject.addConstrainObjects()
      • VivadoProject.addFiles()
      • VivadoProject.boardDesign()
      • VivadoProject.close()
      • VivadoProject.create()
      • VivadoProject.get()
      • VivadoProject.implemAll()
      • VivadoProject.listFileGroups()
      • VivadoProject.listIpmplementations()
      • VivadoProject.listRuns()
      • VivadoProject.listSynthesis()
      • VivadoProject.open()
      • VivadoProject.run()
      • VivadoProject.setIpRepoPaths()
      • VivadoProject.setPart()
      • VivadoProject.setTargetLangue()
      • VivadoProject.setTop()
      • VivadoProject.synthAll()
      • VivadoProject.updateAllCompileOrders()
      • VivadoProject.writeBitstream()
  • hwtBuildsystem.vivado.api.tcl module
    • VivadoBDOpsTCL
      • VivadoBDOpsTCL.connect_bd_intf_net()
      • VivadoBDOpsTCL.connect_bd_net()
      • VivadoBDOpsTCL.create_bd_cell()
      • VivadoBDOpsTCL.create_bd_design()
      • VivadoBDOpsTCL.create_bd_port()
      • VivadoBDOpsTCL.get_bd_cells()
      • VivadoBDOpsTCL.get_bd_intf_pins()
      • VivadoBDOpsTCL.get_bd_intf_ports()
      • VivadoBDOpsTCL.get_bd_pins()
      • VivadoBDOpsTCL.get_bd_ports()
      • VivadoBDOpsTCL.make_wrapper()
      • VivadoBDOpsTCL.open_bd_design()
      • VivadoBDOpsTCL.regenerate_bd_layout()
      • VivadoBDOpsTCL.save_bd_design()
      • VivadoBDOpsTCL.write_bd_tcl()
    • VivadoFSOpsTCL
      • VivadoFSOpsTCL.cd()
      • VivadoFSOpsTCL.file
      • VivadoFSOpsTCL.ls()
      • VivadoFSOpsTCL.pwd()
    • VivadoHdlOps
      • VivadoHdlOps.get_ports()
    • VivadoProjectOpsTCL
      • VivadoProjectOpsTCL.add_files()
      • VivadoProjectOpsTCL.close_project()
      • VivadoProjectOpsTCL.create_project()
      • VivadoProjectOpsTCL.generate_target()
      • VivadoProjectOpsTCL.ip_repo_paths
      • VivadoProjectOpsTCL.launch_runs()
      • VivadoProjectOpsTCL.open_project()
      • VivadoProjectOpsTCL.remove_files()
      • VivadoProjectOpsTCL.reset_run()
      • VivadoProjectOpsTCL.run()
      • VivadoProjectOpsTCL.update_compile_order()
      • VivadoProjectOpsTCL.update_ip_catalog()
      • VivadoProjectOpsTCL.wait_on_run()
    • VivadoTCL
      • VivadoTCL.group
      • VivadoTCL.set_property()
      • VivadoTCL.sim
      • VivadoTCL.source()
      • VivadoTCL.start_gui()
      • VivadoTCL.synth_design()
  • hwtBuildsystem.vivado.api.unit module
    • VivadoBoardDesignUnit
      • VivadoBoardDesignUnit.create()
      • VivadoBoardDesignUnit.get()
      • VivadoBoardDesignUnit.pin()
      • VivadoBoardDesignUnit.set()
• hwtBuildsystem.vivado.logParser package
  • Submodules
  • hwtBuildsystem.vivado.logParser.synthesis module
    • VivadoSynthesisLogParser
      • VivadoSynthesisLogParser.RE_SECTION_NAME_UNDERLINE
      • VivadoSynthesisLogParser.RE_TABLE_HEADER
      • VivadoSynthesisLogParser.RE_TABLE_TOP_LINE
      • VivadoSynthesisLogParser.getBasicResourceReport()
      • VivadoSynthesisLogParser.indexByRowNameColumnName()
      • VivadoSynthesisLogParser.parse()

Submodules

hwtBuildsystem.vivado.config module

class hwtBuildsystem.vivado.config.VivadoConfig

Bases: object

HOME = None

classmethod getExec()

classmethod getHome()

hwtBuildsystem.vivado.executor module

hwtBuildsystem.vivado.metaParser module

hwtBuildsystem.vivado.metaParser.format_option_list(options)

hwtBuildsystem.vivado.metaParser.listChips()

hwtBuildsystem.vivado.part module

class hwtBuildsystem.vivado.part.XilinxPart(family, size, package, speedgrade, grade='c')

Bases: object

Xilinx FPGA model name specification

class Family

Bases: object

atrix7 = '7a'

kintex7 = '7k'

kintexUltrascale = 'ku'

rtKintexUltrascale = 'rk'

spartan7 = '7s'

virtex7 = '7v'

virtexUltrascale = 'vu'

virtexuplus = 'u2'

zynq7000 = '7z'

zynqUltrascale = 'zu'

class Grade

Bases: object

AUTOMOTIVE = 'a'

CUSTOMMER = 'c'

DEFENSE_AND_SPACE = 'q'

class Package

Bases: object

cflva2104 = 'cflva2104'

cflvb2104 = 'cflvb2104'

cflvc2104 = 'cflvc2104'

cl400 = 'cl400'

cl484 = 'cl484'

clg225 = 'clg225'

clg400 = 'clg400'

clg484 = 'clg484'

clg485 = 'clg485'

cna1509 = 'cna1509'

cpg236 = 'cpg236'

cpg238 = 'cpg238'

cpga196 = 'cpga196'

cs324 = 'cs324'

cs325 = 'cs325'

csg324 = 'csg324'

csg325 = 'csg325'

csga225 = 'csga225'

csga324 = 'csga324'

fbg484 = 'fbg484'

fbg676 = 'fbg676'

fbg900 = 'fbg900'

fbv484 = 'fbv484'

fbv676 = 'fbv676'

fbv900 = 'fbv900'

fbva676 = 'fbva676'

fbva900 = 'fbva900'

fbvb900 = 'fbvb900'

ffg1156 = 'ffg1156'

ffg1157 = 'ffg1157'

ffg1158 = 'ffg1158'

ffg1761 = 'ffg1761'

ffg1926 = 'ffg1926'

ffg1927 = 'ffg1927'

ffg1928 = 'ffg1928'

ffg1930 = 'ffg1930'

ffg676 = 'ffg676'

ffg900 = 'ffg900'

ffg901 = 'ffg901'

ffv1156 = 'ffv1156'

ffv1157 = 'ffv1157'

ffv1158 = 'ffv1158'

ffv1761 = 'ffv1761'

ffv1927 = 'ffv1927'

ffv676 = 'ffv676'

ffv900 = 'ffv900'

ffv901 = 'ffv901'

ffva1156 = 'ffva1156'

ffva1517 = 'ffva1517'

ffva1760 = 'ffva1760'

ffva2104 = 'ffva2104'

ffva676 = 'ffva676'

ffvb1156 = 'ffvb1156'

ffvb1517 = 'ffvb1517'

ffvb1760 = 'ffvb1760'

ffvb2104 = 'ffvb2104'

ffvb676 = 'ffvb676'

ffvc1156 = 'ffvc1156'

ffvc1517 = 'ffvc1517'

ffvc1760 = 'ffvc1760'

ffvc2104 = 'ffvc2104'

ffvc900 = 'ffvc900'

ffvd1156 = 'ffvd1156'

ffvd1517 = 'ffvd1517'

ffvd1760 = 'ffvd1760'

ffvd900 = 'ffvd900'

ffve1156 = 'ffve1156'

ffve1517 = 'ffve1517'

ffve1760 = 'ffve1760'

ffve1924 = 'ffve1924'

ffve900 = 'ffve900'

ffvf1517 = 'ffvf1517'

ffvf1760 = 'ffvf1760'

ffvg1517 = 'ffvg1517'

ffvh1760 = 'ffvh1760'

fg484 = 'fg484'

fgg484 = 'fgg484'

fgg676 = 'fgg676'

fgga484 = 'fgga484'

fgga676 = 'fgga676'

fhg1761 = 'fhg1761'

fhga2104 = 'fhga2104'

fhgb2104 = 'fhgb2104'

fhgc2104 = 'fhgc2104'

figd2104 = 'figd2104'

flg1155 = 'flg1155'

flg1925 = 'flg1925'

flg1926 = 'flg1926'

flg1928 = 'flg1928'

flg1930 = 'flg1930'

flg1931 = 'flg1931'

flg1932 = 'flg1932'

flga2104 = 'flga2104'

flga2577 = 'flga2577'

flga2892 = 'flga2892'

flgb2104 = 'flgb2104'

flgb2377 = 'flgb2377'

flgc2104 = 'flgc2104'

flgf1924 = 'flgf1924'

flva1517 = 'flva1517'

flva2104 = 'flva2104'

flvb1760 = 'flvb1760'

flvb2104 = 'flvb2104'

flvc2104 = 'flvc2104'

flvd1517 = 'flvd1517'

flvd1924 = 'flvd1924'

flvf1924 = 'flvf1924'

fsga2577 = 'fsga2577'

fsgd2104 = 'fsgd2104'

fsva3824 = 'fsva3824'

fsvb3824 = 'fsvb3824'

fsve1156 = 'fsve1156'

fsvf1760 = 'fsvf1760'

fsvg1517 = 'fsvg1517'

fsvh1760 = 'fsvh1760'

fsvh1924 = 'fsvh1924'

fsvh2104 = 'fsvh2104'

fsvh2892 = 'fsvh2892'

ftg256 = 'ftg256'

ftgb196 = 'ftgb196'

hcg1155 = 'hcg1155'

hcg1931 = 'hcg1931'

hcg1932 = 'hcg1932'

rb484 = 'rb484'

rb676 = 'rb676'

rf1156 = 'rf1156'

rf1157 = 'rf1157'

rf1158 = 'rf1158'

rf1761 = 'rf1761'

rf1930 = 'rf1930'

rf676 = 'rf676'

rf900 = 'rf900'

rs484 = 'rs484'

sbg484 = 'sbg484'

sbg485 = 'sbg485'

sbv484 = 'sbv484'

sbv485 = 'sbv485'

sbva484 = 'sbva484'

sfva625 = 'sfva625'

sfva784 = 'sfva784'

sfvb784 = 'sfvb784'

sfvc784 = 'sfvc784'

vsva1365 = 'vsva1365'

class Size

Bases: object

h580t = 'h580t'

h870t = 'h870t'

u060 = 'u060'

x1140t = 'x1140t'

x330t = 'x330t'

x415t = 'x415t'

x485t = 'x485t'

x550t = 'x550t'

x690t = 'x690t'

x980t = 'x980t'

class Speedgrade

Bases: object

as_tuple()

name()

hwtBuildsystem.vivado.report module

class hwtBuildsystem.vivado.report.VivadoReport(projectRoot: str, projectName: str, topName: str)

Bases: object

This class is output from hardware synthesis made by vivado All attributes are filenames

parseUtilizationSynth()

setBitstreamFileName(runName='impl_1')

setImplFileNames(runName='impl_1')

setSynthFileNames(runName='synth_1')

hwtBuildsystem.vivado.xdcGen module

class hwtBuildsystem.vivado.xdcGen.PortType

Bases: object

clk = 'clk'

rst = 'rst'

class hwtBuildsystem.vivado.xdcGen.SimpleXDCProp(port, mode)

Bases: object

xdc property setter container

asTcl()

class hwtBuildsystem.vivado.xdcGen.XdcComment(text)

Bases: XdcTextWrapper

tcl xdc comment

class hwtBuildsystem.vivado.xdcGen.XdcIoStandard(port, mode)

Bases: SimpleXDCProp

Io standard of pin thats mean setting of voltage, open-drain etc…

DIFF_HSTL_I = 'DIFF_HSTL_I'

HSTL_I = 'HSTL_I'

HSTL_I_DCI = 'HSTL_I_DCI'

LVCMOS12 = 'LVCMOS12'

LVCMOS15 = 'LVCMOS15'

LVCMOS18 = 'LVCMOS18'

LVCMOS25 = 'LVCMOS25'

class hwtBuildsystem.vivado.xdcGen.XdcLoc(port, mode)

Bases: SimpleXDCProp

class hwtBuildsystem.vivado.xdcGen.XdcPackagePin(port, mode)

Bases: SimpleXDCProp

class hwtBuildsystem.vivado.xdcGen.XdcSlew(port, mode)

Bases: SimpleXDCProp

FAST = 'FAST'

class hwtBuildsystem.vivado.xdcGen.XdcTextWrapper(text)

Bases: object

Wrapper around tcl in text

asTcl()

class hwtBuildsystem.vivado.xdcGen.XdcVccAuxIo(port, mode)

Bases: SimpleXDCProp

DONTCARE = 'DONTCARE'

NORMAL = 'NORMAL'