Source code for hwtBuildsystem.vivado.xdcGen
from hwtBuildsystem.vivado.api.tcl import VivadoTCL
[docs]
class PortType():
clk = "clk"
rst = "rst"
[docs]
class SimpleXDCProp():
"""
xdc property setter container
"""
def __init__(self, port, mode):
self.port = port
self.mode = mode
[docs]
def asTcl(self):
return VivadoTCL.set_property('[' + self.port.get(forHdlWrapper=True) + ']', self._propName, self.mode)
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class XdcVccAuxIo(SimpleXDCProp):
_propName = "VCCAUX_IO"
NORMAL = "NORMAL"
DONTCARE = "DONTCARE"
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class XdcSlew(SimpleXDCProp):
_propName = "SLEW"
FAST = "FAST"
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class XdcLoc(SimpleXDCProp):
_propName = "LOC"
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class XdcPackagePin(SimpleXDCProp):
_propName = 'PACKAGE_PIN'
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class XdcIoStandard(SimpleXDCProp):
"""
Io standard of pin thats mean setting of voltage, open-drain etc...
"""
_propName = "IOSTANDARD"
LVCMOS12 = "LVCMOS12"
LVCMOS15 = "LVCMOS15"
LVCMOS18 = "LVCMOS18"
LVCMOS25 = 'LVCMOS25'
LVCMOS33 = 'LVCMOS33'
HSTL_I_DCI = "HSTL_I_DCI"
DIFF_HSTL_I = "DIFF_HSTL_I"
HSTL_I = "HSTL_I"
# file:///opt/intelFPGA/18.0/quartus/common/help/webhelp/index.htm#reference/glossary/def_iostandard.htm
[docs]
class XdcTextWrapper():
"""Wrapper around tcl in text"""
def __init__(self, text):
self.text = text
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def asTcl(self):
return self.text