hwtBuildsystem.quartus.api package¶

Submodules¶

hwtBuildsystem.quartus.api.project module¶

class hwtBuildsystem.quartus.api.project.QuartusProject(executor: QuartusExecutor, path: str, name: str)[source]¶

Bases: SynthesisToolProject

Attention:: After project is opened the currend directory is changed to

SUFFIX_TO_FILE_TYPE = {'.ip': 'IP_FILE', '.sdc': 'SDC_FILE', '.sv': 'SYSTEMVERILOG_FILE', '.svh': 'VERILOG_INCLUDE_FILE', '.v': 'VERILOG_FILE', '.vh': 'VERILOG_INCLUDE_FILE', '.vhd': 'VHDL_FILE'}¶

addConstrainFiles(files)[source]¶

addFiles(files)[source]¶

close()[source]¶

create()[source]¶

implemAll()[source]¶

setPart(part: IntelPart)[source]¶

Parameters:: part – tuple family, part number e.g (“Cyclone”, “EP1C12F256C6”)

setTop(topName)[source]¶

synthAll()[source]¶

writeBitstream()[source]¶

hwtBuildsystem.quartus.api.tcl module¶

class hwtBuildsystem.quartus.api.tcl.QuartusProjectTCL[source]¶: Bases: CommonTcl