hwtBuildsystem.vivado.api package

exception hwtBuildsystem.vivado.api.ConfigErr

Bases: Exception

class hwtBuildsystem.vivado.api.FILE_TYPE

Bases: object

EDIF = 'EDIF'

NGC = 'NGC'

SYSTEMVERILOG = 'SystemVerilog'

TCL = 'TCL'

VERILOG = 'Verilog'

VERILOG_HEADER = 'Verilog Header'

VHDL = 'VHDL'

VHDL_2008 = 'VHDL 2008'

class hwtBuildsystem.vivado.api.Language

Bases: object

verilog = 'verilog'

vhdl = 'VHDL'

Submodules

hwtBuildsystem.vivado.api.boardDesign module

class hwtBuildsystem.vivado.api.boardDesign.VivadoBoardDesign(project: VivadoProject, name=None)

Bases: object

create()

delete(fromDisk=True)

exist()

exportToTCL(fileName, force=False)

importFromTcl(fileName, refrestTclIfExists=True)

Parameters

refrestIfExists – refresh tcl file from bd before opening design

insertPort(port)

mkWrapper()

open()

regenerateLayout()

setAsTop()

unit(name, ipCore=None) → hwtBuildsystem.vivado.api.unit.VivadoBoardDesignUnit

hwtBuildsystem.vivado.api.net module

class hwtBuildsystem.vivado.api.net.VivadoBoardDesignNet(bd: VivadoBoardDesign, src, dst)

Bases: object

create()

classmethod createMultipleFromDict(bd: VivadoBoardDesign, netDict)

hwtBuildsystem.vivado.api.pin module

class hwtBuildsystem.vivado.api.pin.VivadoBoardDesignPin(bd, name, hasSubIntf=False)

Bases: object

get()

hwtBuildsystem.vivado.api.port module

class hwtBuildsystem.vivado.api.port.VivadoBoardDesignPort(bd, name, direction=None, typ=None, hasSubIntf=False, config=None, width=None, bitIndx=None)

Bases: object

create()

forEachBit(fn)

classmethod fromInterface(interface: hwt.interfaces.std.Signal)

get(forHdlWrapper=False)

hwtBuildsystem.vivado.api.project module

class hwtBuildsystem.vivado.api.project.VivadoProject(executor: VivadoExecutor, path, name)

Bases: hwtBuildsystem.common.project.SynthesisToolProject

SUFFIX_TO_FILE_TYPE = {'.edif': 'EDIF', '.ngc': 'NGC', '.sv': 'SystemVerilog', '.svh': 'Verilog Header', '.tcl': 'TCL', '.v': 'Verilog', '.vh': 'Verilog Header', '.vhd': 'VHDL 2008'}

addConstrainObjects(name, constrains)

addFiles(files)

boardDesign(name) → hwtBuildsystem.vivado.api.boardDesign.VivadoBoardDesign

close()

create(in_memory=False)

get()

implemAll()

listFileGroups()

listIpmplementations()

listRuns()

listSynthesis()

open()

run(jobName: str, to_step: Optional[str] = None)

setIpRepoPaths(paths)

setPart(part: Union[hwtBuildsystem.vivado.part.XilinxPart, str])

setTargetLangue(lang)

setTop(topName)

synthAll()

updateAllCompileOrders()

writeBitstream()

hwtBuildsystem.vivado.api.tcl module

class hwtBuildsystem.vivado.api.tcl.VivadoBDOpsTCL

Bases: object

static connect_bd_intf_net(src: str, dst: str)

static connect_bd_net(src: str, dst: str)

static create_bd_cell(ipId: str, name: str)

static create_bd_design(name: str)

static create_bd_port(name: str, direction: ipCorePackager.constants.DIRECTION, typ: Optional[str] = None, width: Optional[int] = None)

static get_bd_cells(names: List[str])

static get_bd_intf_pins(names: List[str])

static get_bd_intf_ports(names: List[str])

static get_bd_pins(names)

static get_bd_ports(names)

static make_wrapper(bdFile: str)

static open_bd_design(fileName)

static regenerate_bd_layout()

static save_bd_design()

static write_bd_tcl(tclFileName, force=False)

save bd as independent tcl bd has to be saved and opened

class hwtBuildsystem.vivado.api.tcl.VivadoFSOpsTCL

Bases: object

static cd(path: str)

class file

Bases: object

static delete(files, force=True)

static ls()

static pwd()

class hwtBuildsystem.vivado.api.tcl.VivadoHdlOps

Bases: object

static get_ports(portNames)

class hwtBuildsystem.vivado.api.tcl.VivadoProjectOpsTCL

Bases: object

static add_files(files, fileSet=None, norecurse=True)

static close_project()

static create_project(_dir, name, in_memory=False)

Parameters

• in_memory – Create an in-memory project

• name – Project name

• _dir – Directory where the project file is saved

static generate_target(bdFile)

class ip_repo_paths

Bases: object

static add(repoPath)

Multiple add will not cause duplicates

static launch_runs(names: List[str], workerCnt=None, to_step=None, quiet=False)

static open_project(filename: str)

static remove_files(files)

remove from project

static reset_run(name: str)

static run(jobName, workerCnt=None)

static update_compile_order(fileSet)

static update_ip_catalog(rebuild=True, scan_changes=True)

static wait_on_run(run, timeout=None)

class hwtBuildsystem.vivado.api.tcl.VivadoTCL

Bases: hwtBuildsystem.common.tcl.CommonTcl, hwtBuildsystem.vivado.api.tcl.VivadoFSOpsTCL, hwtBuildsystem.vivado.api.tcl.VivadoBDOpsTCL, hwtBuildsystem.vivado.api.tcl.VivadoProjectOpsTCL, hwtBuildsystem.vivado.api.tcl.VivadoHdlOps

python wraps for Vivado TCL commands

class group

Bases: object

static end()

static start()

static set_property(obj, name=None, value=None, valDict=None, valList=None)

class sim

Bases: object

static close()

static launch()

static source(scriptPath, noTrace=True)

static start_gui()

static synth_design(top: str, part: str, quiet=False)

hwtBuildsystem.vivado.api.unit module

class hwtBuildsystem.vivado.api.unit.VivadoBoardDesignUnit(bd: VivadoBoardDesign, ipCore, name)

Bases: object

create()

get()

pin(name, hasSubIntf=False) → hwtBuildsystem.vivado.api.pin.VivadoBoardDesignPin

set(config)