hwtBuildsystem.yosys package

Subpackages

• hwtBuildsystem.yosys.api package
  • Submodules
  • hwtBuildsystem.yosys.api.project module
    • YosysProject
      • YosysProject.SUFFIX_TO_FILE_TYPE
      • YosysProject.addFiles()
      • YosysProject.close()
      • YosysProject.create()
      • YosysProject.implemAll()
      • YosysProject.setPart()
      • YosysProject.setTop()
      • YosysProject.synthAll()
      • YosysProject.writeBitstream()
• hwtBuildsystem.yosys.logParser package
  • Submodules
  • hwtBuildsystem.yosys.logParser.synthesis module
    • YosysSynthesisLogParser
      • YosysSynthesisLogParser.RE_CELLS
      • YosysSynthesisLogParser.RE_INDENT
      • YosysSynthesisLogParser.RE_TABLE_HEADER_LINE
      • YosysSynthesisLogParser.getBasicResourceReport()
      • YosysSynthesisLogParser.parse()

Submodules

hwtBuildsystem.yosys.config module

class hwtBuildsystem.yosys.config.YosysConfig

Bases: object

classmethod getExec()

hwtBuildsystem.yosys.executor module

hwtBuildsystem.yosys.part module

class hwtBuildsystem.yosys.part.LatticePart(family, model, package)

Bases: object

Lattice FPGA model name specification eg. ‘Lattice’, ‘iCE40’, ‘up5k’, ‘sg48’

as_tuple()

hwtBuildsystem.yosys.report module

class hwtBuildsystem.yosys.report.YosysReport(projectRoot: str, projectName: str, topName: str)

Bases: object

This class is output from hardware synthesis made by Intel Quartus

parseUtilizationSynth()

setBitstreamFileName()

setImplLog(text: str)

setSynthLog(text: str)